Nov 18 – 22, 2024
America/New_York timezone

Design, Testing and Performance of a sub-5ps RMS TDC ASIC in 22nm CMOS for LGAD and 4K readout.

Nov 19, 2024, 2:15 PM
15m
262B (Student Union)

262B

Student Union

Parallel Presentation RDC4: Readout and ASICs RDC 04 - Readout and ASICs Parallel Session

Speaker

Si Xie (Fermi National Accelerator Laboratory and Caltech)

Description

We present the design and performance of the DILVERT time-to-digital (TDC) readout chip developed for room temperature and 4K cryogenic operations. The chip simultaneously achieves very low power and picosecond timing resolution when operated in a cryogenic (4K) environment. It features configurable time bins and is an enabling technology for precision timing applications including 4D tracking and quantum communications. We present measurements using charge injection of LGAD signals and achieve time resolution consistent with the 3 ps design specification.

Primary authors

Adam Quinn (Fermilab) Artur Apresyan (Fermi National Accelerator Laboratory) Cristian Pena (Fermi National Accelerator Laboratory) Davide Braga (Fermilab) Si Xie (Fermi National Accelerator Laboratory and Caltech)

Presentation materials