Nov 18 – 22, 2024
America/New_York timezone

Cryogenic CMOS Amplifiers for Enhanced Sensitivity in the CMB-S4 Experiment

Nov 19, 2024, 1:45 PM
15m
262B (Student Union)

262B

Student Union

Parallel Presentation RDC4: Readout and ASICs RDC 04 - Readout and ASICs Parallel Session

Speaker

Aldo Pena-Perez (SLAC National Lab | Stanford University)

Description

The next-generation Cosmic Microwave Background Stage 4 (CMB-S4) survey aims to map the Cosmic Microwave Background with unprecedented sensitivity, probing key areas of fundamental physics such as inflation, exotic light relics, and dark energy. To meet these ambitious objectives, the experiment will deploy approximately 500,000 photon-noise-limited superconducting transition edge sensors (TES) across various large and small aperture telescopes. These TES will operate within cryogenic receivers, requiring multiplexing through low-temperature superconducting quantum interference device (SQUID)-based electronics. SQUID are ultra-sensitive detectors that measure faint magnetic fields, essential for capturing weak CMB signals from the early universe.

To optimize the cryogenic readout for the SQUIDs, the TID-ID Integrated Circuits group at SLAC National Lab has developed R&D amplifiers using state-of-the-art CMOS technologies, including 28 nm and 22 nm FDSOI. These mini-ASICs are engineered for deep cryogenic operation at 4 K, with potential performance at 1 K, allowing for direct interfacing with low-noise SQUIDs housed in cryocoolers. This integration significantly enhances the system's sensitivity by reducing noise and enabling more precise signal detection. By placing the readout electronics at cryogenic temperatures rather than room temperature, the system benefits from minimized cabling, improved signal-to-noise ratio (SNR), and a reduced thermal load on the cryostat. Supported by the LDRD program, these low-power, ultra-low-noise amplifiers, with simulated noise as low as 0.3 nV/√Hz, will be characterized in 2025, laying the groundwork for future System-on-Chip (SoC) ASIC developments tailored for extreme cryogenic environments.

Primary authors

Aldo Pena-Perez (SLAC National Lab | Stanford University) Angelo Dragone (SLAC National Lab | Stanford University) Gunther Haller (SLAC National Lab | Stanford University) Llorenc Fanals-i-Batllori (SLAC National Lab | Stanford University) Lorenzo Rota (SLAC National Lab | Stanford University) Shawn Henderson (SLAC National Lab | Stanford University) Zeeshan Ahmed (SLAC National Lab | Stanford University)

Presentation materials