Speaker
Josef Sorenson
(University of New Mexico)
Description
Detectors at future colliders will require timing precision on the order of 10 ps. Towards this goal, we’ve developed a low-power, high-speed prototype ASIC named MetaRock. MetaRock is an evolution of the Pebbles ASIC. As compared to its predecessor, MetaRock has improvements in the layout of the Pebbles analog front-end to reduce parasitic capacitances and enhance timing resolution. An on chip test bench consisting of a charge injection circuit and a second high-resolution (20 ps LSB) TDC are used for evaluating the performance of the AFE. Results are validated with an external high-resolution (4 ps LSB) TDC. We will present the AFE and testbed architecture and summarize the test results of the MetaRock prototype.
Primary authors
Amanda Krieger
(LBNL)
Maurice Garcia-Sciveres
(Lawrence Berkeley national laboratory)
Timon Heim
(Lawrence Berkeley National Lab)
Carl Grace
(LBNL)
Josef Sorenson
(University of New Mexico)
Zhicai Zhang
(LBNL)
Kennedy Caisley
(LBNL)
