Speaker
Description
Monolithic active pixel sensors (MAPS) are crucial for current and future High Energy Physics detectors, due to their minimal material budget, low power consumption and low cost per unit area. Following the successful deployment of the first detector based on MAPS at CERN (ALICE Inner Tracker System 2, ITS2) adopting the TowerJazz 180 nm imaging CMOS technology, the investigation of the TPSCo 65 nm imaging technology was started. This effort is done in the framework of the CERN EP R&D program, in synergy with the ALICE experiment, interested in developing a wafer-scale, stitched sensor for its ITS3 upgrade to replace the inner layers of the ITS2. The smaller feature size of this 65 nm technology is crucial to match the requirements of pixel pitch, time resolution, output data rate and radiation hardness of future HEP detectors. In addition, this technology allows the fabrication of wafer-scale sensors on larger wafers (300 mm instead of 200 mm for the 180 nm process) and reduce the material budget to less than 0.09% X$_0$, due to the inclusion of all power and data connections on chip.
This presentation will give an overview of this R&D program, highlighting the path from the design and characterization of test structures to qualify the technology for use in HEP, to the development of wafer-scale sensors. Efficient operation was demonstrated before and after irradiation (up to 10$^{15}$ 1 MeV neq/cm$^2$ at room temperature) for pixel pitches between 10 and 25 µm, and sensor timing resolution down to ~ 65 ps RMS was obtained for a 10 µm pitch. The H2M (Hybrid-to-Monolithic) ASIC implemented a hybrid pixel architecture in a monolithic sensor at 35 µm pitch and revealed some sensitivity to circuit layout for larger pixel pitches. Different approaches to stitching were investigated in the MOSS and MOST sensors, in preparation for the design of the MOSAIX, the wafer-scale stitched chip for the ITS3 upgrade based on 22.8 x 20.8 µm$^2$ pixels. This R&D activity has raised interest in this technology and helped gain experience to provide support and access to the TPSCo 65 nm process, fostering further developments in the field of monolithic CMOS sensors. The presentation will end with an outlook on the future challenges of this R&D in view of ALICE3, FCC-ee, and other applications.
