Speaker
Description
There is increasing interest in deploying sophisticated machine learning (ML) algorithms as part of the real-time data processing and filtering systems of high throughput physics facilities such as the future High Luminosity LHC (HL-LHC). To satisfy the strict latency and data processing constraints imposed by such facilities, ML algorithms can be deployed on FPGAs to perform real-time computation. Device manufacturers have recently introduced dedicated reprogrammable architectures that are highly optimized for low-latency real-time inference tasks that use common ML tools such as neural networks. In this talk, we will explore the use and benchmarking of Xilinx’s “AI-Engine” architectures and the associated software development kit workflows for prototyping novel algorithms for FPGAs. Specifically, we present work towards deploying convolutional neural networks (CNNs) on the FPGAs planned for use in the ATLAS experiment’s data filtering and acquisition upgrade to perform pattern recognition tasks to classify and select hadronic jets produced by moderately Lorentz-boosted top quarks. Using this CNN as a case study, we compare the hls4ml and Vitis-AI workflows for deploying these algorithms on FPGAs. We benchmark the latencies and resource usage across various candidate FPGA target devices, ML architectures, and AI-Engine usage.
