Speaker
Description
In this talk we will present CHARMS250 and CHARMS10, next-generation cryogenic front-end application specific integrated circuits (ASICs) designed in a 65 nm process for low-noise readout of charge or light signals generated within noble liquid time projection chambers (TPCs). Both ASICs are designed for operation at temperatures ranging from room temperature down to liquid nitrogen temperature, i.e., 77 K, with large capacitance detectors (up to hundreds of picofarads), with multiple channels of charge amplification stages with gain programmable in the range of ~ 4– 25 mV/fC, pulse shaping filter stages with programmable pulse peaking time, and either direct readout or through single-ended or differential buffers. The design of CHARMS250 has evolved from the LArASIC chip, which was manufactured in a 180 nm process and has been selected as the first component in the 3-ASIC readout solution for Phase I of the Deep Underground Neutrino Experiment (DUNE). CHARMS250 provides shortest pulse peaking time of 250 ns, that is two times smaller than the shortest pulse peaking time provided by LArASIC, with the same power consumption as LArASIC, i.e., 6-11 mW per channel, depending on the choice of the output buffering, and a highly linear voltage readout for input charges up to 300 fC. On the other hand, CHARMS10 features a new front-end design that allows achieving shortest pulse peaking time of 10 ns, without degradation of the output linearity. Additionally, features such as local generation of bias voltages and extended digital assistance of analog functions provided over an I2C interface are included in both ASICs for improved robustness against process variability. Potential applications for CHARMS250 and CHARMS10 include light/charge readout of the Far Detector (FD) 3/4 in Phase II of DUNE, charge readout in the future circular lepton collider (FCC-ee), light readout in nEXO, and the silicon-based active target and liquid xenon calorimeters in PIONEER.
