Nov 18 – 22, 2024
America/New_York timezone

An Ultra-Low-Voltage, 16-Channel Current DAC ASIC in 22nm FDSOI for Cryogenic SQUID Biasing

Nov 19, 2024, 1:30 PM
15m
262B (Student Union)

262B

Student Union

Parallel Presentation RDC4: Readout and ASICs RDC 04 - Readout and ASICs Parallel Session

Speakers

Suyash Pati Tripathi (University of Toronto) Davide Braga (Fermi National Accelerator Laboratory)

Description

In this work, we present a sixteen-channel, ultra low-voltage (≤ 0.1 V analog supply) current DAC designed in 22nm FDSOI technology for biasing SQUIDs. The ASIC integrates eight 6-bit DACs and eight 8-bit DACs, programmed through a simple serial interface. It operates effectively across a wide temperature range, from 300K to 4K, by using the back-gate bias to counteract threshold voltage variations across temperature. The DACs output current range is 0.25 mA and 1.25 mA for the 6-bit and 8-bit DACs, respectively. Measurement results at both cryo and room temperature demonstrate excellent performance, with DNL below 0.5 LSB for the 8-bit DAC and below 0.25 LSB for the 6-bit DAC.

Primary author

Suyash Pati Tripathi (University of Toronto)

Co-authors

Davide Braga (Fermi National Accelerator Laboratory) Manuel B. Valentin (Northwestern University) Paul M. Rubinov (Fermi National Accelerator Laboratory) Louis Dal Monte (Fermi National Accelerator Laboratory) Farah Fahim (Fermi National Accelerator Laboratory)

Presentation materials

There are no materials yet.