Speaker
Description
Embedded Field Programmable Gate Array (eFPGA) technology enables the integration of reconfigurable logic within an Application-Specific Integrated Circuit (ASIC). This methodology combines the low power consumption and efficiency of ASICs with the flexibility of FPGA configuration, making it particularly useful for machine learning applications in the data processing pipeline of future collider experiments. The open-source framework "FABulous" was used to integrate eFPGAs into a custom ASIC design, which was then fabricated and validated through testing. The potential of an eFPGA to function as a front-end readout chip was evaluated using data from simulations of high-energy particles traversing a silicon pixel sensor. A machine learning classifier, designed to reduce sensor data at the source, was synthesized and deployed onto the eFPGA. This proof-of-concept successfully replicated the expected algorithmic outcomes on the eFPGA with complete accuracy. We will present the performance results of our eFPGA implementation, share our lessons learned, and discuss our ongoing eFPGA R&D efforts, along with its future role in collider detector readout applications.
